<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>To see the actual file transmitted to Xilinx, please click <A HREF="./usage_statistics_webtalk.xml">here</A>.<BR><BR><HR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
  <TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>2086221</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Mon Feb  5 11:09:01 2024</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>Vivado v2017.4 (64-bit)</TD>
  <TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>7dda00c5e16048beb275483a49dfdc30</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>2</TD>
  <TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>f8176f10911950478f9bf5a4728b3ca6</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>f8176f10911950478f9bf5a4728b3ca6</TD>
  <TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>TRUE</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>xc7z010</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>zynq</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>clg400</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>-1</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>Vivado</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>Intel(R) Core(TM) i5-8300H CPU @ 2.30GHz</TD>
  <TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>2304 MHz</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Microsoft Windows 8 or later , 64-bit</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release  (build 9200)</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>17.000 GB</TD>
  <TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
<TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>gui_handlers</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>addsrcwizard_specify_hdl_netlist_block_design=1</TD>
   <TD>addsrcwizard_specify_or_create_constraint_files=1</TD>
   <TD>addsrcwizard_specify_simulation_specific_hdl_files=1</TD>
   <TD>basedialog_cancel=10</TD>
</TR><TR ALIGN='LEFT'>   <TD>basedialog_ok=10</TD>
   <TD>basedialog_yes=2</TD>
   <TD>cmdmsgdialog_ok=3</TD>
   <TD>constraintschooserpanel_create_file=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>coretreetablepanel_core_tree_table=3</TD>
   <TD>createconstraintsfilepanel_file_name=1</TD>
   <TD>createsrcfiledialog_file_name=5</TD>
   <TD>debugwizard_find_nets_to_add=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>debugwizard_sample_of_data_depth=1</TD>
   <TD>filesetpanel_file_set_panel_tree=114</TD>
   <TD>filtertoolbar_hide_all=1</TD>
   <TD>filtertoolbar_show_all=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>flownavigatortreepanel_flow_navigator_tree=43</TD>
   <TD>logmonitor_monitor=3</TD>
   <TD>msgtreepanel_message_view_tree=14</TD>
   <TD>msgview_error_messages=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>msgview_information_messages=1</TD>
   <TD>pacommandnames_add_sources=7</TD>
   <TD>pacommandnames_simulation_live_break=8</TD>
   <TD>pacommandnames_simulation_live_run=4</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_simulation_live_run_all=4</TD>
   <TD>pacommandnames_simulation_relaunch=13</TD>
   <TD>pacommandnames_simulation_run_behavioral=7</TD>
   <TD>projecttab_close_design=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>projecttab_reload=1</TD>
   <TD>rdiviews_waveform_viewer=508</TD>
   <TD>saveprojectutils_save=1</TD>
   <TD>simpleoutputproductdialog_generate_output_products_immediately=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>simulationobjectspanel_simulation_objects_tree_table=4</TD>
   <TD>simulationscopespanel_simulate_scope_table=38</TD>
   <TD>srcchooserpanel_add_hdl_and_netlist_files_to_your_project=1</TD>
   <TD>srcchooserpanel_create_file=4</TD>
</TR><TR ALIGN='LEFT'>   <TD>srcchooserpanel_scan_and_add_rtl_include_files_into=1</TD>
   <TD>syntheticagettingstartedview_recent_projects=1</TD>
   <TD>waveformnametree_waveform_name_tree=58</TD>
   <TD>waveformview_goto_time_0=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>xpg_tabbedpane_tabbed_pane=1</TD>
</TR>  </TABLE>
  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>java_command_handlers</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>addsources=7</TD>
   <TD>coreview=1</TD>
   <TD>customizecore=1</TD>
   <TD>debugwizardcmdhandler=5</TD>
</TR><TR ALIGN='LEFT'>   <TD>editdelete=1</TD>
   <TD>recustomizecore=1</TD>
   <TD>runbitgen=2</TD>
   <TD>runsynthesis=5</TD>
</TR><TR ALIGN='LEFT'>   <TD>showview=1</TD>
   <TD>simulationbreak=8</TD>
   <TD>simulationrelaunch=12</TD>
   <TD>simulationrun=6</TD>
</TR><TR ALIGN='LEFT'>   <TD>simulationrunall=4</TD>
   <TD>simulationrunfortime=4</TD>
   <TD>toolssettings=1</TD>
   <TD>viewtaskprojectmanager=6</TD>
</TR><TR ALIGN='LEFT'>   <TD>viewtasksimulation=2</TD>
</TR>  </TABLE>
</TR><TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>other_data</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>guimode=2</TD>
</TR>  </TABLE>
  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>project_data</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>constraintsetcount=1</TD>
   <TD>core_container=false</TD>
   <TD>currentimplrun=impl_1</TD>
   <TD>currentsynthesisrun=synth_1</TD>
</TR><TR ALIGN='LEFT'>   <TD>default_library=xil_defaultlib</TD>
   <TD>designmode=RTL</TD>
   <TD>export_simulation_activehdl=1</TD>
   <TD>export_simulation_ies=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>export_simulation_modelsim=1</TD>
   <TD>export_simulation_questa=1</TD>
   <TD>export_simulation_riviera=1</TD>
   <TD>export_simulation_vcs=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>export_simulation_xsim=1</TD>
   <TD>implstrategy=Vivado Implementation Defaults</TD>
   <TD>launch_simulation_activehdl=0</TD>
   <TD>launch_simulation_ies=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_modelsim=0</TD>
   <TD>launch_simulation_questa=0</TD>
   <TD>launch_simulation_riviera=0</TD>
   <TD>launch_simulation_vcs=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_xsim=30</TD>
   <TD>simulator_language=Mixed</TD>
   <TD>srcsetcount=2</TD>
   <TD>synthesisstrategy=Vivado Synthesis Defaults</TD>
</TR><TR ALIGN='LEFT'>   <TD>target_language=Verilog</TD>
   <TD>target_simulator=XSim</TD>
   <TD>totalimplruns=2</TD>
   <TD>totalsynthesisruns=2</TD>
</TR>  </TABLE>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>unisim_transformation</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>post_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufg=2</TD>
    <TD>fdce=30</TD>
    <TD>fdpe=2</TD>
    <TD>gnd=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>ibuf=2</TD>
    <TD>lut1=1</TD>
    <TD>lut2=4</TD>
    <TD>lut4=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut5=6</TD>
    <TD>lut6=15</TD>
    <TD>mmcme2_adv=1</TD>
    <TD>obuf=3</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcc=3</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>pre_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufg=2</TD>
    <TD>fdce=30</TD>
    <TD>fdpe=2</TD>
    <TD>gnd=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>ibuf=3</TD>
    <TD>lut1=1</TD>
    <TD>lut2=4</TD>
    <TD>lut4=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut5=6</TD>
    <TD>lut6=15</TD>
    <TD>mmcme2_adv=1</TD>
    <TD>obuf=3</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcc=3</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>power_opt_design</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options_spo</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-cell_types=default::all</TD>
    <TD>-clocks=default::[not_specified]</TD>
    <TD>-exclude_cells=default::[not_specified]</TD>
    <TD>-include_cells=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bram_ports_augmented=2</TD>
    <TD>bram_ports_newly_gated=0</TD>
    <TD>bram_ports_total=4</TD>
    <TD>flow_state=default</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_augmented=0</TD>
    <TD>slice_registers_newly_gated=0</TD>
    <TD>slice_registers_total=2225</TD>
    <TD>srls_augmented=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>srls_newly_gated=0</TD>
    <TD>srls_total=195</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>ip_statistics</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clk_wiz_v5_4_3_0/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>clkin1_period=20.000</TD>
    <TD>clkin2_period=10.0</TD>
    <TD>clock_mgr_type=NA</TD>
    <TD>component_name=system_clk</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>enable_axi=0</TD>
    <TD>feedback_source=FDBK_AUTO</TD>
    <TD>feedback_type=SINGLE</TD>
</TR><TR ALIGN='LEFT'>    <TD>iptotal=1</TD>
    <TD>manual_override=false</TD>
    <TD>num_out_clk=1</TD>
    <TD>primitive=MMCM</TD>
</TR><TR ALIGN='LEFT'>    <TD>use_dyn_phase_shift=false</TD>
    <TD>use_dyn_reconfig=false</TD>
    <TD>use_inclk_stopped=false</TD>
    <TD>use_inclk_switchover=false</TD>
</TR><TR ALIGN='LEFT'>    <TD>use_locked=true</TD>
    <TD>use_max_i_jitter=false</TD>
    <TD>use_min_o_jitter=false</TD>
    <TD>use_phase_alignment=true</TD>
</TR><TR ALIGN='LEFT'>    <TD>use_power_down=false</TD>
    <TD>use_reset=false</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>labtools_ila_v6_00_a/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>all_probe_same_mu=true</TD>
    <TD>all_probe_same_mu_cnt=1</TD>
    <TD>c_adv_trigger=false</TD>
    <TD>c_data_depth=2048</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_en_strg_qual=false</TD>
    <TD>c_input_pipe_stages=0</TD>
    <TD>c_num_of_probes=9</TD>
    <TD>c_probe0_type=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_probe0_width=8</TD>
    <TD>c_probe1_type=0</TD>
    <TD>c_probe1_width=8</TD>
    <TD>c_probe2_type=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_probe2_width=1</TD>
    <TD>c_probe3_type=0</TD>
    <TD>c_probe3_width=1</TD>
    <TD>c_probe4_type=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_probe4_width=1</TD>
    <TD>c_probe5_type=0</TD>
    <TD>c_probe5_width=1</TD>
    <TD>c_probe6_type=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_probe6_width=1</TD>
    <TD>c_probe7_type=0</TD>
    <TD>c_probe7_width=1</TD>
    <TD>c_probe8_type=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_probe8_width=1</TD>
    <TD>c_trigin_en=0</TD>
    <TD>c_trigout_en=0</TD>
    <TD>component_name=u_ila_0_CV</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>labtools_xsdbm_v3_00_a/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_bscan_mode=false</TD>
    <TD>c_bscan_mode_with_core=false</TD>
    <TD>c_clk_input_freq_hz=300000000</TD>
    <TD>c_en_bscanid_vec=false</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_enable_clk_divider=false</TD>
    <TD>c_num_bscan_master_ports=0</TD>
    <TD>c_two_prim_mode=false</TD>
    <TD>c_use_ext_bscan=false</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_user_scan_chain=1</TD>
    <TD>c_xsdb_num_slaves=1</TD>
    <TD>component_name=dbg_hub_CV</TD>
    <TD>core_container=NA</TD>
</TR><TR ALIGN='LEFT'>    <TD>iptotal=1</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_drc</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-append=default::[not_specified]</TD>
    <TD>-checks=default::[not_specified]</TD>
    <TD>-fail_on=default::[not_specified]</TD>
    <TD>-force=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-format=default::[not_specified]</TD>
    <TD>-messages=default::[not_specified]</TD>
    <TD>-name=default::[not_specified]</TD>
    <TD>-return_string=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-ruledecks=default::[not_specified]</TD>
    <TD>-upgrade_cw=default::[not_specified]</TD>
    <TD>-waived=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>rtstat-10=1</TD>
    <TD>zps7-1=1</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_methodology</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-append=default::[not_specified]</TD>
    <TD>-checks=default::[not_specified]</TD>
    <TD>-fail_on=default::[not_specified]</TD>
    <TD>-force=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-format=default::[not_specified]</TD>
    <TD>-messages=default::[not_specified]</TD>
    <TD>-name=default::[not_specified]</TD>
    <TD>-return_string=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-waived=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>ckld-2=1</TD>
    <TD>pdrc-190=16</TD>
    <TD>timing-17=31</TD>
    <TD>timing-27=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>xdcb-5=19</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_power</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-advisory=default::[not_specified]</TD>
    <TD>-append=default::[not_specified]</TD>
    <TD>-file=[specified]</TD>
    <TD>-format=default::text</TD>
</TR><TR ALIGN='LEFT'>    <TD>-hier=default::power</TD>
    <TD>-l=default::[not_specified]</TD>
    <TD>-name=default::[not_specified]</TD>
    <TD>-no_propagation=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-return_string=default::[not_specified]</TD>
    <TD>-rpx=[specified]</TD>
    <TD>-verbose=default::[not_specified]</TD>
    <TD>-vid=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-xpe=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>airflow=250 (LFM)</TD>
    <TD>ambient_temp=25.0 (C)</TD>
    <TD>bi-dir_toggle=12.500000</TD>
    <TD>bidir_output_enable=1.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>board_layers=8to11 (8 to 11 Layers)</TD>
    <TD>board_selection=medium (10&quot;x10&quot;)</TD>
    <TD>bram=0.000519</TD>
    <TD>clocks=0.004841</TD>
</TR><TR ALIGN='LEFT'>    <TD>confidence_level_clock_activity=High</TD>
    <TD>confidence_level_design_state=High</TD>
    <TD>confidence_level_device_models=High</TD>
    <TD>confidence_level_internal_activity=Medium</TD>
</TR><TR ALIGN='LEFT'>    <TD>confidence_level_io_activity=Low</TD>
    <TD>confidence_level_overall=Low</TD>
    <TD>customer=TBD</TD>
    <TD>customer_class=TBD</TD>
</TR><TR ALIGN='LEFT'>    <TD>devstatic=0.094262</TD>
    <TD>die=xc7z010clg400-1</TD>
    <TD>dsp_output_toggle=12.500000</TD>
    <TD>dynamic=0.114212</TD>
</TR><TR ALIGN='LEFT'>    <TD>effective_thetaja=11.5</TD>
    <TD>enable_probability=0.990000</TD>
    <TD>family=zynq</TD>
    <TD>ff_toggle=12.500000</TD>
</TR><TR ALIGN='LEFT'>    <TD>flow_state=routed</TD>
    <TD>heatsink=none</TD>
    <TD>i/o=0.002552</TD>
    <TD>input_toggle=12.500000</TD>
</TR><TR ALIGN='LEFT'>    <TD>junction_temp=27.4 (C)</TD>
    <TD>logic=0.000546</TD>
    <TD>mgtavcc_dynamic_current=0.000000</TD>
    <TD>mgtavcc_static_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>mgtavcc_total_current=0.000000</TD>
    <TD>mgtavcc_voltage=1.000000</TD>
    <TD>mgtavtt_dynamic_current=0.000000</TD>
    <TD>mgtavtt_static_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>mgtavtt_total_current=0.000000</TD>
    <TD>mgtavtt_voltage=1.200000</TD>
    <TD>mgtvccaux_dynamic_current=0.000000</TD>
    <TD>mgtvccaux_static_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>mgtvccaux_total_current=0.000000</TD>
    <TD>mgtvccaux_voltage=1.800000</TD>
    <TD>mmcm=0.104991</TD>
    <TD>netlist_net_matched=NA</TD>
</TR><TR ALIGN='LEFT'>    <TD>off-chip_power=0.000000</TD>
    <TD>on-chip_power=0.208474</TD>
    <TD>output_enable=1.000000</TD>
    <TD>output_load=5.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>output_toggle=12.500000</TD>
    <TD>package=clg400</TD>
    <TD>pct_clock_constrained=2.000000</TD>
    <TD>pct_inputs_defined=50</TD>
</TR><TR ALIGN='LEFT'>    <TD>platform=nt64</TD>
    <TD>process=typical</TD>
    <TD>ram_enable=50.000000</TD>
    <TD>ram_write=50.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>read_saif=False</TD>
    <TD>set/reset_probability=0.000000</TD>
    <TD>signal_rate=False</TD>
    <TD>signals=0.000764</TD>
</TR><TR ALIGN='LEFT'>    <TD>simulation_file=None</TD>
    <TD>speedgrade=-1</TD>
    <TD>static_prob=False</TD>
    <TD>temp_grade=commercial</TD>
</TR><TR ALIGN='LEFT'>    <TD>thetajb=9.3 (C/W)</TD>
    <TD>thetasa=0.0 (C/W)</TD>
    <TD>toggle_rate=False</TD>
    <TD>user_board_temp=25.0 (C)</TD>
</TR><TR ALIGN='LEFT'>    <TD>user_effective_thetaja=11.5</TD>
    <TD>user_junc_temp=27.4 (C)</TD>
    <TD>user_thetajb=9.3 (C/W)</TD>
    <TD>user_thetasa=0.0 (C/W)</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccadc_dynamic_current=0.000000</TD>
    <TD>vccadc_static_current=0.020000</TD>
    <TD>vccadc_total_current=0.020000</TD>
    <TD>vccadc_voltage=1.800000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccaux_dynamic_current=0.058362</TD>
    <TD>vccaux_io_dynamic_current=0.000000</TD>
    <TD>vccaux_io_static_current=0.000000</TD>
    <TD>vccaux_io_total_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccaux_io_voltage=1.800000</TD>
    <TD>vccaux_static_current=0.005475</TD>
    <TD>vccaux_total_current=0.063837</TD>
    <TD>vccaux_voltage=1.800000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccbram_dynamic_current=0.000033</TD>
    <TD>vccbram_static_current=0.000276</TD>
    <TD>vccbram_total_current=0.000309</TD>
    <TD>vccbram_voltage=1.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccint_dynamic_current=0.006775</TD>
    <TD>vccint_static_current=0.003883</TD>
    <TD>vccint_total_current=0.010658</TD>
    <TD>vccint_voltage=1.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco12_dynamic_current=0.000000</TD>
    <TD>vcco12_static_current=0.000000</TD>
    <TD>vcco12_total_current=0.000000</TD>
    <TD>vcco12_voltage=1.200000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco135_dynamic_current=0.000000</TD>
    <TD>vcco135_static_current=0.000000</TD>
    <TD>vcco135_total_current=0.000000</TD>
    <TD>vcco135_voltage=1.350000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco15_dynamic_current=0.000000</TD>
    <TD>vcco15_static_current=0.000000</TD>
    <TD>vcco15_total_current=0.000000</TD>
    <TD>vcco15_voltage=1.500000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco18_dynamic_current=0.000000</TD>
    <TD>vcco18_static_current=0.000000</TD>
    <TD>vcco18_total_current=0.000000</TD>
    <TD>vcco18_voltage=1.800000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco25_dynamic_current=0.000000</TD>
    <TD>vcco25_static_current=0.000000</TD>
    <TD>vcco25_total_current=0.000000</TD>
    <TD>vcco25_voltage=2.500000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco33_dynamic_current=0.000713</TD>
    <TD>vcco33_static_current=0.001000</TD>
    <TD>vcco33_total_current=0.001713</TD>
    <TD>vcco33_voltage=3.300000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco_ddr_dynamic_current=0.000000</TD>
    <TD>vcco_ddr_static_current=0.000000</TD>
    <TD>vcco_ddr_total_current=0.000000</TD>
    <TD>vcco_ddr_voltage=1.500000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco_mio0_dynamic_current=0.000000</TD>
    <TD>vcco_mio0_static_current=0.000000</TD>
    <TD>vcco_mio0_total_current=0.000000</TD>
    <TD>vcco_mio0_voltage=1.800000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco_mio1_dynamic_current=0.000000</TD>
    <TD>vcco_mio1_static_current=0.000000</TD>
    <TD>vcco_mio1_total_current=0.000000</TD>
    <TD>vcco_mio1_voltage=1.800000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccpaux_dynamic_current=0.000000</TD>
    <TD>vccpaux_static_current=0.010330</TD>
    <TD>vccpaux_total_current=0.010330</TD>
    <TD>vccpaux_voltage=1.800000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccpint_dynamic_current=0.000000</TD>
    <TD>vccpint_static_current=0.016954</TD>
    <TD>vccpint_total_current=0.016954</TD>
    <TD>vccpint_voltage=1.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccpll_dynamic_current=0.000000</TD>
    <TD>vccpll_static_current=0.003000</TD>
    <TD>vccpll_total_current=0.003000</TD>
    <TD>vccpll_voltage=1.800000</TD>
</TR><TR ALIGN='LEFT'>    <TD>version=2017.4</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_utilization</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clocking</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufgctrl_available=32</TD>
    <TD>bufgctrl_fixed=0</TD>
    <TD>bufgctrl_used=2</TD>
    <TD>bufgctrl_util_percentage=6.25</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufhce_available=48</TD>
    <TD>bufhce_fixed=0</TD>
    <TD>bufhce_used=0</TD>
    <TD>bufhce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufio_available=8</TD>
    <TD>bufio_fixed=0</TD>
    <TD>bufio_used=0</TD>
    <TD>bufio_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufmrce_available=4</TD>
    <TD>bufmrce_fixed=0</TD>
    <TD>bufmrce_used=0</TD>
    <TD>bufmrce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufr_available=8</TD>
    <TD>bufr_fixed=0</TD>
    <TD>bufr_used=0</TD>
    <TD>bufr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>mmcme2_adv_available=2</TD>
    <TD>mmcme2_adv_fixed=0</TD>
    <TD>mmcme2_adv_used=1</TD>
    <TD>mmcme2_adv_util_percentage=50.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>plle2_adv_available=2</TD>
    <TD>plle2_adv_fixed=0</TD>
    <TD>plle2_adv_used=0</TD>
    <TD>plle2_adv_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>dsp</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>dsps_available=80</TD>
    <TD>dsps_fixed=0</TD>
    <TD>dsps_used=0</TD>
    <TD>dsps_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>io_standard</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>blvds_25=0</TD>
    <TD>diff_hstl_i=0</TD>
    <TD>diff_hstl_i_18=0</TD>
    <TD>diff_hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_hstl_ii_18=0</TD>
    <TD>diff_hsul_12=0</TD>
    <TD>diff_mobile_ddr=0</TD>
    <TD>diff_sstl135=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl135_r=0</TD>
    <TD>diff_sstl15=0</TD>
    <TD>diff_sstl15_r=0</TD>
    <TD>diff_sstl18_i=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl18_ii=0</TD>
    <TD>hstl_i=0</TD>
    <TD>hstl_i_18=0</TD>
    <TD>hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>hstl_ii_18=0</TD>
    <TD>hsul_12=0</TD>
    <TD>lvcmos12=0</TD>
    <TD>lvcmos15=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvcmos18=0</TD>
    <TD>lvcmos25=0</TD>
    <TD>lvcmos33=1</TD>
    <TD>lvds_25=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvttl=0</TD>
    <TD>mini_lvds_25=0</TD>
    <TD>mobile_ddr=0</TD>
    <TD>pci33_3=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>ppds_25=0</TD>
    <TD>rsds_25=0</TD>
    <TD>sstl135=0</TD>
    <TD>sstl135_r=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>sstl15=0</TD>
    <TD>sstl15_r=0</TD>
    <TD>sstl18_i=0</TD>
    <TD>sstl18_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>tmds_33=0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>memory</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>block_ram_tile_available=60</TD>
    <TD>block_ram_tile_fixed=0</TD>
    <TD>block_ram_tile_used=1.5</TD>
    <TD>block_ram_tile_util_percentage=2.50</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb18_available=120</TD>
    <TD>ramb18_fixed=0</TD>
    <TD>ramb18_used=1</TD>
    <TD>ramb18_util_percentage=0.83</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb18e1_only_used=1</TD>
    <TD>ramb36_fifo_available=60</TD>
    <TD>ramb36_fifo_fixed=0</TD>
    <TD>ramb36_fifo_used=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb36_fifo_util_percentage=1.67</TD>
    <TD>ramb36e1_only_used=1</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>primitives</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bscane2_functional_category=Others</TD>
    <TD>bscane2_used=1</TD>
    <TD>bufg_functional_category=Clock</TD>
    <TD>bufg_used=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>carry4_functional_category=CarryLogic</TD>
    <TD>carry4_used=42</TD>
    <TD>fdce_functional_category=Flop &amp; Latch</TD>
    <TD>fdce_used=200</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdpe_functional_category=Flop &amp; Latch</TD>
    <TD>fdpe_used=42</TD>
    <TD>fdre_functional_category=Flop &amp; Latch</TD>
    <TD>fdre_used=1965</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdse_functional_category=Flop &amp; Latch</TD>
    <TD>fdse_used=18</TD>
    <TD>ibuf_functional_category=IO</TD>
    <TD>ibuf_used=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut1_functional_category=LUT</TD>
    <TD>lut1_used=40</TD>
    <TD>lut2_functional_category=LUT</TD>
    <TD>lut2_used=146</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut3_functional_category=LUT</TD>
    <TD>lut3_used=211</TD>
    <TD>lut4_functional_category=LUT</TD>
    <TD>lut4_used=251</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut5_functional_category=LUT</TD>
    <TD>lut5_used=189</TD>
    <TD>lut6_functional_category=LUT</TD>
    <TD>lut6_used=566</TD>
</TR><TR ALIGN='LEFT'>    <TD>mmcme2_adv_functional_category=Clock</TD>
    <TD>mmcme2_adv_used=1</TD>
    <TD>muxf7_functional_category=MuxFx</TD>
    <TD>muxf7_used=14</TD>
</TR><TR ALIGN='LEFT'>    <TD>obuf_functional_category=IO</TD>
    <TD>obuf_used=3</TD>
    <TD>ramb18e1_functional_category=Block Memory</TD>
    <TD>ramb18e1_used=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb36e1_functional_category=Block Memory</TD>
    <TD>ramb36e1_used=1</TD>
    <TD>ramd32_functional_category=Distributed Memory</TD>
    <TD>ramd32_used=36</TD>
</TR><TR ALIGN='LEFT'>    <TD>rams32_functional_category=Distributed Memory</TD>
    <TD>rams32_used=12</TD>
    <TD>srl16e_functional_category=Distributed Memory</TD>
    <TD>srl16e_used=95</TD>
</TR><TR ALIGN='LEFT'>    <TD>srlc16e_functional_category=Distributed Memory</TD>
    <TD>srlc16e_used=2</TD>
    <TD>srlc32e_functional_category=Distributed Memory</TD>
    <TD>srlc32e_used=98</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>slice_logic</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>f7_muxes_available=8800</TD>
    <TD>f7_muxes_fixed=0</TD>
    <TD>f7_muxes_used=14</TD>
    <TD>f7_muxes_util_percentage=0.16</TD>
</TR><TR ALIGN='LEFT'>    <TD>f8_muxes_available=4400</TD>
    <TD>f8_muxes_fixed=0</TD>
    <TD>f8_muxes_used=0</TD>
    <TD>f8_muxes_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_distributed_ram_fixed=0</TD>
    <TD>lut_as_distributed_ram_used=24</TD>
    <TD>lut_as_logic_available=17600</TD>
    <TD>lut_as_logic_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_used=1267</TD>
    <TD>lut_as_logic_util_percentage=7.20</TD>
    <TD>lut_as_memory_available=6000</TD>
    <TD>lut_as_memory_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_used=140</TD>
    <TD>lut_as_memory_util_percentage=2.33</TD>
    <TD>lut_as_shift_register_fixed=0</TD>
    <TD>lut_as_shift_register_used=116</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_flip_flop_available=35200</TD>
    <TD>register_as_flip_flop_fixed=0</TD>
    <TD>register_as_flip_flop_used=2225</TD>
    <TD>register_as_flip_flop_util_percentage=6.32</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_latch_available=35200</TD>
    <TD>register_as_latch_fixed=0</TD>
    <TD>register_as_latch_used=0</TD>
    <TD>register_as_latch_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_luts_available=17600</TD>
    <TD>slice_luts_fixed=0</TD>
    <TD>slice_luts_used=1407</TD>
    <TD>slice_luts_util_percentage=7.99</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_available=35200</TD>
    <TD>slice_registers_fixed=0</TD>
    <TD>slice_registers_used=2225</TD>
    <TD>slice_registers_util_percentage=6.32</TD>
</TR><TR ALIGN='LEFT'>    <TD>fully_used_lut_ff_pairs_fixed=6.32</TD>
    <TD>fully_used_lut_ff_pairs_used=76</TD>
    <TD>lut_as_distributed_ram_fixed=0</TD>
    <TD>lut_as_distributed_ram_used=24</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_available=17600</TD>
    <TD>lut_as_logic_fixed=0</TD>
    <TD>lut_as_logic_used=1267</TD>
    <TD>lut_as_logic_util_percentage=7.20</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_available=6000</TD>
    <TD>lut_as_memory_fixed=0</TD>
    <TD>lut_as_memory_used=140</TD>
    <TD>lut_as_memory_util_percentage=2.33</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_shift_register_fixed=0</TD>
    <TD>lut_as_shift_register_used=116</TD>
    <TD>lut_ff_pairs_with_one_unused_flip_flop_fixed=116</TD>
    <TD>lut_ff_pairs_with_one_unused_flip_flop_used=658</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_ff_pairs_with_one_unused_lut_output_fixed=658</TD>
    <TD>lut_ff_pairs_with_one_unused_lut_output_used=730</TD>
    <TD>lut_flip_flop_pairs_available=17600</TD>
    <TD>lut_flip_flop_pairs_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_flip_flop_pairs_used=870</TD>
    <TD>lut_flip_flop_pairs_util_percentage=4.94</TD>
    <TD>slice_available=4400</TD>
    <TD>slice_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_used=692</TD>
    <TD>slice_util_percentage=15.73</TD>
    <TD>slicel_fixed=0</TD>
    <TD>slicel_used=456</TD>
</TR><TR ALIGN='LEFT'>    <TD>slicem_fixed=0</TD>
    <TD>slicem_used=236</TD>
    <TD>unique_control_sets_used=131</TD>
    <TD>using_o5_and_o6_fixed=131</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o5_and_o6_used=79</TD>
    <TD>using_o5_output_only_fixed=79</TD>
    <TD>using_o5_output_only_used=3</TD>
    <TD>using_o6_output_only_fixed=3</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o6_output_only_used=34</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>specific_feature</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bscane2_available=4</TD>
    <TD>bscane2_fixed=0</TD>
    <TD>bscane2_used=1</TD>
    <TD>bscane2_util_percentage=25.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>capturee2_available=1</TD>
    <TD>capturee2_fixed=0</TD>
    <TD>capturee2_used=0</TD>
    <TD>capturee2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>dna_port_available=1</TD>
    <TD>dna_port_fixed=0</TD>
    <TD>dna_port_used=0</TD>
    <TD>dna_port_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>efuse_usr_available=1</TD>
    <TD>efuse_usr_fixed=0</TD>
    <TD>efuse_usr_used=0</TD>
    <TD>efuse_usr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>frame_ecce2_available=1</TD>
    <TD>frame_ecce2_fixed=0</TD>
    <TD>frame_ecce2_used=0</TD>
    <TD>frame_ecce2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>icape2_available=2</TD>
    <TD>icape2_fixed=0</TD>
    <TD>icape2_used=0</TD>
    <TD>icape2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>startupe2_available=1</TD>
    <TD>startupe2_fixed=0</TD>
    <TD>startupe2_used=0</TD>
    <TD>startupe2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>xadc_available=1</TD>
    <TD>xadc_fixed=0</TD>
    <TD>xadc_used=0</TD>
    <TD>xadc_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>router</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>actual_expansions=1303499</TD>
    <TD>bogomips=0</TD>
    <TD>bram18=1</TD>
    <TD>bram36=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufg=0</TD>
    <TD>bufr=0</TD>
    <TD>congestion_level=0</TD>
    <TD>ctrls=131</TD>
</TR><TR ALIGN='LEFT'>    <TD>dsp=0</TD>
    <TD>effort=2</TD>
    <TD>estimated_expansions=1876800</TD>
    <TD>ff=2225</TD>
</TR><TR ALIGN='LEFT'>    <TD>global_clocks=2</TD>
    <TD>high_fanout_nets=1</TD>
    <TD>iob=5</TD>
    <TD>lut=1470</TD>
</TR><TR ALIGN='LEFT'>    <TD>movable_instances=4212</TD>
    <TD>nets=4424</TD>
    <TD>pins=22727</TD>
    <TD>pll=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>router_runtime=0.000000</TD>
    <TD>router_timing_driven=1</TD>
    <TD>threads=2</TD>
    <TD>timing_constraints_exist=1</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>synthesis</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-assert=default::[not_specified]</TD>
    <TD>-bufg=default::12</TD>
    <TD>-cascade_dsp=default::auto</TD>
    <TD>-constrset=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-control_set_opt_threshold=default::auto</TD>
    <TD>-directive=default::default</TD>
    <TD>-fanout_limit=default::10000</TD>
    <TD>-flatten_hierarchy=default::rebuilt</TD>
</TR><TR ALIGN='LEFT'>    <TD>-fsm_extraction=default::auto</TD>
    <TD>-gated_clock_conversion=default::off</TD>
    <TD>-generic=default::[not_specified]</TD>
    <TD>-include_dirs=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-keep_equivalent_registers=default::[not_specified]</TD>
    <TD>-max_bram=default::-1</TD>
    <TD>-max_bram_cascade_height=default::-1</TD>
    <TD>-max_dsp=default::-1</TD>
</TR><TR ALIGN='LEFT'>    <TD>-max_uram=default::-1</TD>
    <TD>-max_uram_cascade_height=default::-1</TD>
    <TD>-mode=default::default</TD>
    <TD>-name=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-no_lc=default::[not_specified]</TD>
    <TD>-no_srlextract=default::[not_specified]</TD>
    <TD>-no_timing_driven=default::[not_specified]</TD>
    <TD>-part=xc7z010clg400-1</TD>
</TR><TR ALIGN='LEFT'>    <TD>-resource_sharing=default::auto</TD>
    <TD>-retiming=default::[not_specified]</TD>
    <TD>-rtl=default::[not_specified]</TD>
    <TD>-rtl_skip_constraints=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-rtl_skip_ip=default::[not_specified]</TD>
    <TD>-seu_protect=default::none</TD>
    <TD>-sfcu=default::[not_specified]</TD>
    <TD>-shreg_min_size=default::3</TD>
</TR><TR ALIGN='LEFT'>    <TD>-top=spi_top</TD>
    <TD>-verilog_define=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>elapsed=00:00:32s</TD>
    <TD>hls_ip=0</TD>
    <TD>memory_gain=513.578MB</TD>
    <TD>memory_peak=808.594MB</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>xsim</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-sim_mode=behavioral</TD>
    <TD>-sim_type=default::</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
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